Scrub through 152 years of this role's history — from when it first emerged, through every wave of technology that reshaped it, to the cited projections for where it's heading next.
Slide rule + hand calculation + physical prototyping (electrification era)
Vacuum tube + graphical network analysis (power system era)
Transistor + early digital computing (Bell Labs, Texas Instruments era)
MATLAB/Simulink + CAD/CAE power tools + offshore foundry model (systems integration era)
IEEE unification + SPICE circuit simulation (analog and digital design era)
CHIPS Act + AI-datacenter power systems + IRA electrification (infrastructure super-cycle)
19001925195019752000now
Drag the dot, click anywhere on the track, or use ← → arrow keys (Shift for 10-year jumps, PgUp/PgDn for 25).
2026
Known today as Electrical Engineer (BLS SOC 17-2071, distinct from Electronics Engineers 17-2072)
US Employment
192K
BLS OEWS 2024 employment baseline as cited in the O*NET current edition and used as the anchor for BLS 2024-34 employment projections. The modest recovery 2019-2024 reflects two offsetting forces: CHIPS Act-related semiconductor fab projects and AI-datacenter power-system demand pulling headcount up; continued offshoring of manufacturing-side EE work pulling it down. The BLS National Employment Matrix projects growth to 205,700 by 2034 (+7.2%, 13,800 net new jobs over the decade).
Median Annual Wage
$111,910
Source: BLS-OEWS
Tool of the era · CHIPS Act + AI-datacenter power systems + IRA electrification (infrastructure super-cycle)
Three simultaneous policy-and-capital shocks reshaped the demand picture for US electrical engineers in 2022-2025:
(1) CHIPS and Science Act (August 9, 2022): $52.7B in semiconductor manufacturing subsidies; TSMC committed to a second Arizona fab (announced $6.6B federal grant post-passage), Intel secured $8.5B for Ohio and Arizona, Samsung received $6.4B for Texas. BLS projects semiconductor fabrication employment growing 15.1% 2024-34. Each new fab requires hundreds of process and facilities electrical engineers for three to five years of construction.
(2) AI datacenter buildout: Microsoft announced $80B+ in AI infrastructure spending for FY2025; Meta committed $60B+ in 2025; Amazon committed $100B+ across multi-year datacenter expansion. A hyperscale datacenter at 100MW of critical IT load requires tens of millions of watts of power distribution infrastructure — medium-voltage switchgear, UPS systems, backup generation, grounding systems — that must be designed by electrical engineers with PE licenses. BLS projects solar electric power generation employment growing 184% and wind 79.7% through 2034, both of which require grid-interconnection electrical engineering.
(3) Inflation Reduction Act (August 16, 2022): $369B in climate provisions, including ITC extensions for solar, EV charger credits, heat pump incentives. Grid modernization for bidirectional residential power flows (rooftop solar, vehicle-to-grid) requires distribution-system electrical engineers to redesign protection coordination, power quality, and control systems that were designed for one-directional power flow.
In parallel, Synopsys launched Synopsys.ai Copilot in November 2023 — an LLM-based generative AI assistant for chip design, built on OpenAI models via Microsoft — and presented a five-level autonomy roadmap toward fully autonomous chip design at the March 2025 SNUG conference.
BLS National Employment Matrix projects +7.2% growth for 17-2071 (192,000 → 205,700) over 2024-34, with the strongest growth in solar (+184%), wind (+79.7%), and semiconductor manufacturing (+15.1%) subsectors. The solar and wind numbers are small in absolute terms (1,200 and 400 engineers respectively); the datacenter power-systems and semiconductor-fab demand is larger and structurally sustained through at least 2030.
Projection cone · present → 2034
What credible sources project
Scrub the slider past now to anchor each scenario on the scrubber. The spread you see below is the range of futures credible sources project for this role.
CHIPS Act / AI-datacenter demand scenario
→ 2030
+18%
Curator-constructed optimistic scenario anchored on published capital commitments. CHIPS Act semiconductor fab projects (TSMC AZ, Intel OH, Samsung TX) each require 3-5 years of electrical engineering work for facilities design, power distribution, and commissioning — collectively representing $200B+ in fab construction investment and demand for 5,000-10,000 EE-years of fab-construction engineering. AI-datacenter hyperscaler commitments (Microsoft $80B+ FY2025, Meta $60B+, Amazon $100B+ multi-year) each require electrical engineers for power-delivery design at the scale of small electric utilities. IRA electrification (grid modernization for bidirectional power flows, EV charging infrastructure, utility-scale storage interconnection) adds further sustained demand. If all three demand streams materialize simultaneously through 2030, the BLS baseline projection (+7.2%) likely understates peak demand. This is the optimistic tail of the uncertainty cone; treat as an upper bound, not a forecast.
McKinsey Global Institute (2023)
→ 2030
+10%
McKinsey's July 2023 "Generative AI and the Future of Work in America" places STEM occupations — which include electrical engineers — in the positive-growth scenario through 2030 even after accounting for AI-driven productivity gains. STEM occupations are net beneficiaries in the McKinsey model because (a) generative AI raises the ceiling on what a STEM worker can design and analyze, (b) AI-driven productivity growth creates demand for more STEM work rather than less (more projects become feasible), and (c) engineering skill is complementary to AI deployment, not substituted by it. The +10% midpoint is a curator interpretation within the McKinsey STEM band (+5% to +15%); the specific 17-2071 number is not broken out in the public report.
BLS National Employment Matrix 2024-34
→ 2034
+7%
BLS Employment Projections 2024-34 cycle, the most current published projection for SOC 17-2071. Baseline employment: 192,000 (2024). Projected employment: 205,700 (2034). Net change: 13,800 (+7.2%, described by BLS as "much faster than average"). Annual job openings: approximately 11,700 (new positions + replacement need). Strongest growth subsectors: solar electric power generation (+184%), wind electric power generation (+79.7%), semiconductor and electronic component manufacturing (+15.1%), professional/scientific/technical services (+3.4%). The BLS projections use an industry-occupation employment matrix with productivity-adjusted demand; they do not model speculative AI-automation scenarios, so this projection likely understates the upside from CHIPS Act fab construction and AI-datacenter demand that were still being announced at time of publication.
Frey & Osborne (2013)
→ 2033
-10%
Gaussian-process classifier on O*NET task features. Frey & Osborne rated Electrical Engineers among the occupations with the LOWEST probability of computerisation in their 702-occupation dataset — conventionally cited at approximately 0.10 (10%) probability, placing the occupation in the lowest quintile. The bottleneck factors cited are: high "creativity" scores (novel solutions to interdisciplinary engineering problems), complex "human factors" (site-specific engineering judgment, regulatory sign-off, client interaction), and the physical-environment dependence of much electrical engineering work (power systems on specific sites, datacenter power distribution). The -10% figure here represents the implied employment ceiling if F&O's probability were fully realized (which F&O did not claim). Employment has grown +22% from 2010 to 2024, validating the low-risk classification. F&O did not model EDA/AI chip-design tools specifically.
Eloundou et al. — "GPTs are GPTs" (2023)
→ 2028
-20%
GPT-4 task-by-task LLM exposure labeling on O*NET tasks for Architecture and Engineering occupations. Electrical engineers have moderate LLM exposure: documentation, specifications, and technical report writing are all text-based tasks an LLM can accelerate; circuit simulation and code-generation for HDLs (Verilog/VHDL) are areas where LLMs can generate first drafts. However, core EE work — physical system design, electromagnetic field analysis, safety-critical sign-off, on-site commissioning, interdisciplinary integration between mechanical/electrical/software systems — is not LLM-accessible. The -20% estimate reflects the moderate-exposure interpretation of the Eloundou β score for the engineering occupational group, consistent with "exposure" (capability, not substitution) at approximately 20-30% of work tasks. Treat as ceiling on task-automation, not floor on job loss.
Today, in this role
What's shifting in the work right now
The historical view above shows how this role has moved. This is the present-day detail: which AI tools are picking up which tasks, where the edge still is, and the natural directions this work can grow.
What's changing in your day
Three parts of your work where AI is already doing real lifting — and what stays yours.
AI is sitting alongside you here
Run autonomous SoC implementation using Cadence Cerebrus AI Studio or Synopsys DSO.ai: specify performance, power, and area (PPA) targets; let reinforcement-learning engines explore the design-space across place-and-route, clock tree synthesis, and timing closure; review AI-generated implementation results against signoff constraints before releasing to fabrication.[7],[12]
AI engines explore billions of design-space configurations and return a ranked shortlist, but PPA targets that matter — especially power vs. performance trade-offs for your specific application domain (mobile, server, automotive) — require engineering judgment to set correctly. Develop deep familiarity with the cost functions these tools optimize and learn to recognize when an "optimal" AI implementation is optimizing the wrong objective for your product context.
AI is sitting alongside you here
Design and lay out printed circuit boards using Cadence Allegro X AI: provide component netlist, power/ground requirements, signal integrity constraints, and layer stackup; use AI global placement to evaluate thousands of placement strategies simultaneously; review the AI-generated placement for thermal clearances, EMI management, and assembly-process constraints before approving routing.[13],[14]
Allegro X AI compresses three-day placement tasks to 75 minutes and reduces wire length by 12%, but the AI does not model mechanical assembly constraints, thermal interface material placement, or EMC shielding requirements. Build a systematic pre-placement checklist covering these non-electrical constraints so your review of AI-generated layouts is structured and repeatable, not a free-form hunt for hidden problems.
AI is sitting alongside you here
Design and verify digital IC and SoC implementations end-to-end using the Siemens Fuse EDA AI Agent (launched March 2026): orchestrate automated flows spanning RTL coding (Catapult), functional verification (Questa One), place-and-route (Aprisa), physical verification DRC (Calibre), and 3D IC power/ground analysis; review agent execution plans before each stage and audit AI-generated violation clusters before sign-off.[8],[15]
Fuse EDA AI Agent orchestrates full-chip flows across Aprisa, Calibre, and Questa, but the agent requires the engineer to validate its execution plan at each major handoff — especially at physical verification sign-off, where DRC violations in safety-critical silicon (automotive, aerospace) have liability implications. Learn to read Calibre Vision AI violation clusters critically: understand which violation types represent genuine risk vs. known waivers, and maintain a documented waiver policy your team can audit.
Where this role is heading
Natural next steps for someone with your foundation — not exits, evolutions.
A direction you could grow
Architectural and Engineering Managers
Senior electrical engineers who develop strong program management, vendor governance, and AI tool evaluation skills are well-positioned to move into Engineering Manager roles. This transition is especially timely as organizations need managers who can evaluate and govern the rapidly expanding AI EDA toolset — deciding which Cadence, Synopsys, or Siemens AI platforms to invest in, setting sign-off review standards for AI-generated designs, and building team capability in AI-augmented workflows. Bloomberg Intelligence projects AI adds $6B to the EDA market through 2030; organizations need engineering leaders who can translate this into competitive advantage. Engineering Managers retain technical credibility while operating at budget, headcount, and roadmap scope that faces minimal AI displacement pressure.
What you'd add
· Engineering program management: scope, schedule, and budget ownership; earned value tracking; milestone planning for multi-year hardware programs